1. Field of the Invention
The present invention relates to a semiconductor device having a semiconductor chip mounted on a package substrate, and particularly relates to a semiconductor device having a structure for improving connection reliability of bump electrodes formed on a back surface of the package substrate, and manufacturing method thereof.
2. Description of Related Art
Semiconductor devices have been conventionally used in which a large number of bump electrodes are formed on a back surface of a package substrate and a semiconductor chip is mounted on the package substrate. Such semiconductor devices particularly have a problem of fracture of bump electrodes located in the vicinity of an outer portion of the semiconductor chip among the bump electrodes on the package substrate. Generally, in the semiconductor chip, a difference between coefficients of thermal expansion is larger than that of the package substrate or resin, and therefore some of the bump electrodes are prone to damage due to stress induced at a boundary portion of the semiconductor chip. Particularly, since the coefficients of thermal expansion largely differ between a portion where the semiconductor chip exists and a portion where the semiconductor chip does not exist, the damage to the bump electrodes increases in regions close to corner portions of the semiconductor chip relative to other regions. Accordingly, in order to improve mounting reliability of the semiconductor device, measures to suppress the damage to the bump electrodes in the vicinity of the corner portions of the semiconductor chip are desired.
Various methods have been conventionally proposed to improve connection strength of the bump electrodes in semiconductor devices. For example, a method for improving the connection strength by forming bump electrodes of large size in corner portions of a dielectric substrate (for example, see Patent Reference 1), a method for inducing uniform stress on the bump electrodes by forming the bump electrodes having a curved contour at their outer edges on a substrate (for example, see Patent Reference 2), and a method for preventing the fracture due to stress concentration on certain bump electrodes by arranging the bump electrodes in a concentric manner on the package substrate (for example, see Patent Reference 3) have been proposed.    Patent Reference 1: Laid-open Japanese Patent Publication No. 2001-210749    Patent Reference 2: Laid-open Japanese Patent Publication No. Hei 9-162531    Patent Reference 3: Laid-open Japanese Patent Publication No. Hei 11-307564
However, according to the above conventional methods, the effect to prevent the fracture due to the stress concentration on the bump electrodes is restrictive, and is insufficient for improving the connection reliability of the bump electrodes. That is, the above conventional methods enable to suppress the stress concentration on the bump electrodes in peripheral portions including the corner portions of the package substrate, however it has been discovered that the fracture due to the stress concentration on the bump electrodes is actually prone to occur mainly at the bump electrodes immediately under corner portions of the semiconductor chip, instead of corner portions of the package substrate.
Problems related to the above connection reliability will be described with reference to FIGS. 10, 11A and 11B. As shown in FIG. 10, a plurality of bump electrodes 101 arranged in a matrix form is formed on a back surface of a package substrate 100, and positions overlapping an outline of a semiconductor chip 102 mounted on an opposite surface are shown with a dotted line. Among the plurality of bump electrodes 101 shown in FIG. 10, four bump electrodes 101a located immediately under corner portions of the semiconductor chip 102 are especially prone to fracture due to stress. FIGS. 11A and 11B are diagrams schematically showing behaviors of a semiconductor device including the package substrate 100 under temperature fluctuation. A semiconductor chip 102 mounted on a central region of the top surface of the package substrate 100 is electrically connected to the bump electrodes 101 through wires 103, a wiring structure (not shown) of the package substrate 100 and lands 104 respectively in this order.
The semiconductor chip 102 has a coefficient of thermal expansion which is smaller than that of the package substrate 100 or upper resin 105. Thus, in FIGS. 11A and 11B, a region R1 in which the semiconductor chip 102 is arranged is difficult to expand due to the temperature fluctuation. On the other hand, a region R2 in which the semiconductor chip 102 is not arranged is relatively prone to expand due to the temperature fluctuation. Accordingly, under the temperature fluctuation, stress occurs due to expansion and contraction of the regions R1 and R2, and there appear two cases, one of which is an upward concave deformation as shown in FIG. 11A, and the other of which is an upward convex deformation as shown in FIG. 11B. In these cases, bump electrodes 101a formed immediately under a boundary between the regions R1 and R2 is a base point of the expansion and contraction of the package substrate 100, and therefore is directly affected by the stress. Particularly, the bump electrodes 101a immediately under the corner portions of the semiconductor chip 102 are prone to fracture due to the stress.
Since the above conventional methods do not focus attention on whether or not the semiconductor chip 102 exists, the damage to the bump electrodes 101a becomes large immediately under the corner portions of the semiconductor chip 102 so that the probability of the fracture inevitably increases. Also, in the above conventional methods, the region where the bump electrodes 101 are not arranged is provided, for example, in a peripheral portion of the package substrate 100, which is a disadvantage in terms of arrangement density of the bump electrodes 101. Since a semiconductor device having multiple pins and narrow pitch has been strongly demanded, it becomes a problem to solve to implement measures without hindering a high density arrangement of a large number of bump electrodes.